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em78p156el otp rom em78p156el 8-bit micro-controller version 1.3
em78p156el otp rom specification revision history version content 1 . 0 i n i t i a l v e r s i o n 1.1 change set up tim e period 04/19/2002 1.2 change power on reset content change isb1 & icc3 current range 07/01/2003 1.3 add the device characteri stic at section 6.3 07/29/2004 application note an-001 em78p156e v.s. em78p156 on the dc characteristics and program timing an-002 em78p156e v.s. em78p156 on the initialized value for registers an-003 q & a on em78p156e this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 2
em78p156el otp rom 1. general description em78p15 6el is an 8-bit microp ro ce ssor d e si gne d a nd d e velop e d with lo w-po wer a nd high -speed cm os techn o logy. it is equi ppe d with 1k* 1 3 - bits ele c tri c al one time prog ramm a b le read on ly memory (otp-ro m ). it provides a protecti on bit to prev ent use r ?s cod e in the otp memory from being intruded. 6 option bits are also avail able to meet user?s requirements. with its otp-rom feature, the em 78p156el is able to offer a convenient way of developi ng a nd verifying use r ? s prog ra ms. mo reove r , user can ta ke a d vanta g e of emc writ e r to e a sily p r ogram hi s de velopme n t code. this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 3
em78p156el otp rom 2. features ? operating voltage range : 2.3v~5.5v ? operating temperature range: 0
em78p156el otp rom * 20 pin ssop 209mil : em78p156elas * 20 pin ssop 209mil : EM78P156ELKM ? 99.9% single instruction cycle commands ? the transient point of system fr equency between hxt and lxt is around 400khz this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 5
em78p156el otp rom 3. pin assignments tc c vdd vss p5 0 p5 1 p5 3 p6 0 / in t p6 1 p6 2 p6 3 p 6 4 p5 2 /r e s et osci osco p6 7 p6 6 p6 5 em 78 p15 6 elp em 7 8 p 1 5 6 e l m 1 2 3 4 5 6 7 8 9 16 15 14 13 12 11 10 17 18 tcc vdd vs s p5 0 p5 1 p5 3 p6 0 / i n t p6 1 p6 2 p6 3 p 6 4 p5 2 /r eset osci osc o p6 7 p6 6 p6 5 em78p156elas 1 2 3 4 5 6 7 8 9 16 15 14 13 12 11 10 17 18 nc nc 20 19 tc c vd d vs s p50 p51 p5 3 p6 0 / i n t p6 1 p6 2 p 6 3 p64 p5 2 /reset osci osco p67 p66 p65 e m 7 8p156 el km 1 2 3 4 5 6 7 8 9 16 15 14 13 12 11 10 17 18 20 19 vs s v dd fig. 1 pin assignment t a ble 1 em78p156elp and em78p156elm pin description symbol pin no. type function vdd 14 - * power supply. o s c i 1 6 i * xtal type: crystal input terminal or external clock input pin. * erc type: rc oscillator input pin. o s c o 1 5 i / o * xtal type: output terminal for c r ys tal o scill ator or ext e rn al cl ock in put pin. * rc type: instruction clock output. * external clock signal input. t c c 3 i * the real time clo c k/count er (with s c hm itt trigger i npu t pin), mu st b e tied t o vdd or vss if not in us e. / r e s e t 4 i * input pin wit h schmitt trig ger. if this pi n remai n s at lo gic lo w, the controll er will also remain in reset condition. p50~p53 17, 18, 1, 2 i/o * p50~p53 are bi-directional i/o pins. * p50 and p51 can also be defined as the r-option pins. * p50~p52 can be pulled-down by software. p60~p67 6 ~ 1 3 i / o * p60~p67 are bi-directional i/o pins. * these can b e pulled - hig h or ca n be ope n-d r ain by sof t ware pro g ra mming . * p60~p63 can also be pulled-down by software. /int 6 i * external interrupt pin triggered by falling edge. v s s 5 - * g r o u n d . this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 6
em78p156el otp rom t a ble 2 em78p156elas pin description symbol pin no. type function vdd 15 - * power supply. o s c i 1 7 i * xtal type: crystal input terminal or external clock input pin. * erc type: rc oscillator input pin. o s c o 1 6 i / o * xtal type: output terminal for c r y s tal o scill ator or extern al cl ock in put pin. * rc type: instruction clock output. * external clock signal input. t c c 4 i * the real time clock/count er (with sch m itt trigger inp u t pin), must be tied to vdd or vss if not in us e. / r e s e t 5 i * input pin wit h schmitt trig ger. if this pi n remai n s at lo gic lo w, the controll er will also remain in reset condition. p50~p53 18, 19, 2, 3 i/o * p50~p53 are bi-directional i/o pins. * p50 and p51 can also be defined as the r-option pins. * p50~p52 can be pulled-down by software. p60~p67 7 ~ 1 4 i / o * p60~p67 are bi-directional i/o pins. * these ca n b e pulled - hi gh or can be o p e n -d rain by software pro g ra mming. * p60~p63 can also be pulled-down by software. /int 7 i * external interrupt pin triggered by falling edge. v s s 6 - * g r o u n d . t a ble 3 EM78P156ELKM pin description symbol pin no. type function vdd 15,16 - * power supply. o s c i 1 8 i * xtal type: crystal input terminal or external clock input pin. * erc type: rc oscillator input pin. o s c o 1 7 i / o * xtal type: output terminal for c r ys tal o scill ator or ext e rn al cl ock in put pin. * rc type: instruction clock output. * external clock signal input. t c c 3 i * the real time clo c k/count er (with s c hm itt trigger i npu t pin), mu st b e tied t o vdd or vss if not in us e. / r e s e t 4 i * input pin wit h schmitt trig ger. if this pi n remai n s at lo gic lo w, the controll er will also remain in reset condition. p50~p53 19, 20, 1, 2 i/o * p50~p53 are bi-directional i/o pins. * p50 and p51 can also be defined as the r-option pins. * p50~p52 can be pulled-down by software. p60~p67 7 ~ 1 4 i / o * p60~p67 are bi-directional i/o pins. * these can b e pulled - hig h or ca n be ope n-d r ain by sof t ware pro g ra mming . * p60~p63 can also be pulled-down by software. /int 7 i * external interrupt pin triggered by falling edge. vss 5, 6 - * ground. this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 7
em78p156el otp rom 4. function description in t e rr up t c ontr o l l e r ro m ins t r u c tion re g i ste r in st ru c t io n decod e r r2 al u sta c k ac c r3 r4 o s c i l l a t or /t im ing co n t ro l wd t t i me r p r es ca le r r1 (t c c ) ram d a ta & co ntro l bu s os ci os co / r es et tcc / int i/ o po r t 6 io c6 r6 p 6 0 //i nt p61 p6 2 p63 p6 4 p6 5 p66 p67 i/ o po r t 5 io c5 r5 p5 0 p5 1 p5 2 p5 3 io c a fig. 2 function block diagram 4.1 operational registers 1. r0 (indirect addressing register) r0 i s not a p h ysically impl emente d re gi ster. its maj o r function i s to perfo rm a s a n indi re ct add re ssi ng pointe r . any instructio n u s ing r0 a s a pointe r a c tua lly accesse s data poi nted by the ram select register (r4). 2. r1 (time clock /counter) ? increa sed b y an external sign al edg e, whi c h is d e fin ed by te bit (co n t-4) thro ugh the tcc pin, or by t he inst ruct ion cy cle clock. ? writable and readable as any other registers. ? defined by resetting pab(cont-3). ? the prescaler is assigned to tcc, if the pab bit (cont-3) is reset. ? the contents of the prescaler coun ter will be cl eared only when tcc regi ster is written with a value. this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 8
em78p156el otp rom 3. r2 (program counter) & stack ? depe ndin g on the d e vice type, r2 a n d hardware sta ck are 10 -bit wi de. t he structu r e i s de pi cted in fig.3. ? generating 1024 u 1 3 bits on-chip ot p rom addresse s to the relative prog rammi ng inst ru ction codes. one program page is 1024 words long. ? r2 is set as all "0"s when under reset condition. ? "jmp" instruction allo ws d i re ct loading of the lowe r 1 0 prog ram co unter bits . th us, "jmp" allows pc to go to any location within a page. ? "call" instruction lo ad s the lower 1 0 b i ts of t he pc, and then p c +1 is pu she d in to the stack. thu s , the subroutine entry address can be located anywhere within a page. ? "ret" ("re tl k", "reti") inst ru ction l oad s the p r o g ram co unter with the cont ents of the to p-level st ack. ? "add r2, a" allows the contents of ?a? to be added to the current pc, and the ninth and tenth bits of the pc are cleared. ? "mov r2, a" allows to lo ad an ad dre s s from the "a " registe r to the lower 8 bit s of the pc, and the ninth and tenth bits of the pc are cleared. ? any instructi on that writes to r2 (e .g., "add r2,a", "mov r2,a", "bc r2,6", ??? ?? ) will cause the ninth and tenth bits (a8~a9 ) of the pc to be cleared. thu s , the compute d jump is limited to the first 25 6 locations of a page. ? a ll inst ruct i on ar e sin g le inst ru ct ion c y c le (f cl k/ 2 o r fclk/4 ) exce pt for the instructio n that woul d change the contents of r2. such instruct ion will need one more instruction cycle. pc ( a 9 ~ a0) stac k level 1 stac k level 3 stac k level 2 stac k level 4 stac k level 5 on-c hip p r ogr a m me m o r y 000h 3ffh 008h i n t e rrupt v e c t or u s e r me mo r y s pac e r e se t ve cto r fig. 3 program counter organization this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 9
em78p156el otp rom address r p a ge registers ioc p a ge registers 00 r0 ( i a r ) r e s e r v e 01 r1 (tcc) cont (control register) 02 r2 ( p c ) r e s e r v e 03 r3 (s t a t u s ) r e s e r v e 04 r4 ( r s r ) r e s e r v e 05 r5 (port5) ioc5 (i/o port control register) 06 r6 (port6) ioc6 (i/o port control register) 0 7 r e s e r v e r e s e r v e 0 8 r e s e r v e r e s e r v e 0 9 r e s e r v e r e s e r v e 0 a r e s e r v e ioca (prescaler control register) 0 b r e s e r v e iocb (pull-down register) 0 c r e s e r v e iocc (open-drain control) 0 d r e s e r v e iocd (pull-high control register) 0 e r e s e r v e ioce (wdt control register) 0f rf (interrupt s t atus) iocf (interrupt mask register) 10 ?j 3f general registers fig. 4 dat a memory configuration this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 10
em78p156el otp rom 4. r3 (status register) 7 6 5 4 3 2 1 0 g p 2 g p 1 g p 0 t p z d c c ? bit 0 (c) carry flag ? bit 1 (dc) auxiliary carry flag ? bit 2 (z) zero flag. set to "1" if the result of an arithmetic or logic operation is zero. ? bit 3 (p) power down bit. set to 1 during power on or by a "wdtc" command and reset to 0 by a "slep" command. ? bit 4 (t) time-out bit. set to 1 with the "slep" and "wdt c" comma nd s, or du ring po we r up an d reset to 0 by wdt time-out. ? bit5 ~7 (gp0 ~ 2) general-purpose read/write bits. 5. r4 (ram select register) ? bits 0~5 are used to select registers (address: 00~06, 0f~3f) in the indirect addressing mode. ? bits 6~7 are not used (read only). ? the bits 6~ 7 s e t to ?1? at all time. ? z flag of r3 will set to ?1? when r4 cont ent is equ al to ?3f.? when r4=r4+1, r4 cont ent will select as r0. ? see the configuration of t he data memory in fig. 4. 6. r5 ~ r6 (port 5 ~ port 6) ? r5 and r6 are i/o registers. ? only the lower 4 bits of r5 are available. 7. rf (interrupt status register) 7 6 5 4 3 2 1 0 - - - - - e x i f i c i f t c i f ?1? means interrupt request, and ?0? means no interrupt occurs. ? bit 0 (tcif) tcc overflow interrupt flag. set w hen tcc overflows, reset by software. ? bit 1 (i cif) port 6 input status ch an ge interrupt flag. set when port 6 input chan ge s, re set by software. ? bit 2 (exif) external interrupt flag. set by falli ng edge on /int pin, reset by software. ? bits 3 ~ 7 not used. ? rf can be cleared by instruction but cannot be set. this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 11
em78p156el otp rom ? iocf is the interrupt mask register. ? note that the result of reading rf is the "logic and" of rf and iocf. 8. r10 ~ r3f ? all of these are 8-bit general-purpose registers. 4.2 special purpose registers 1. a (accumulator) ? internal data transfer, or instruction operand holding ? it cannot be addressed. 2. cont (control register) 7 6 5 4 3 2 1 0 - / i n t t s t e p a b p s r 2 p s r 1 p s r 0 ? bit 0 (psr0) ~ bit 2 (psr 2) tcc/wdt prescaler bits. psr2 psr1 psr0 tcc rate wdt rate 0 0 0 1 : 2 1 : 1 0 0 1 1 : 4 1 : 2 0 1 0 1 : 8 1 : 4 0 1 1 1 : 1 6 1 : 8 1 0 0 1 : 3 2 1 : 1 6 1 0 1 1 : 6 4 1 : 3 2 1 1 0 1 : 1 2 8 1 : 6 4 1 1 1 1 : 2 5 6 1 : 1 2 8 ? bit 3 (pab) prescaler assignment bit. 0: tcc 1: wdt ? bit 4 (te) tcc signal edge 0: increment if the transition from low to high takes place on tcc pin 1: increment if the transition from high to low takes place on tcc pin ? bit 5 (ts) tcc signal source 0: int e rnal inst ruct ion cy cle clock 1: transition on tcc pin ? bit 6 (/int) interrupt enable flag 0: masked by disi or hardware interrupt 1: enabled by eni/reti instructions ? bit 7 not used. ? cont register is both readable and writable. this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 12
em78p156el otp rom 3. ioc5 ~ ioc6 (i/o port control register) ? "1" put the relative i/o pin into high impedance, while "0" defines the relative i/o pin as output. ? only the lower 4 bits of ioc5 can be defined. ? ioc5 and ioc6 registers are both readable and writable. 4. ioca (prescaler counter register) ? ioca register is readable. ? the value of ioca is equal to the contents of prescaler counter. ? down counter. 5. iocb (pull-dow n control register) 7 6 5 4 3 2 1 0 / p d 7 / p d 6 / p d 5 / p d 4 - / p d 2 / p d 1 / p d 0 ? bit 0 (/pd0) control bit is used to enable the pull-down of p50 pin. 0: enable internal pull-down 1: disable internal pull-down ? bit 1 (/pd1) control bit is used to enable the pull-down of p51 pin. ? bit 2 (/pd2) control bit is used to enable the pull-down of p52 pin. ? bit 3 not us ed. ? bit 4 (/pd4) control bit is used to enable the pull-down of p60 pin. ? bit 5 (/pd5) control bit is used to enable the pull-down of p61 pin. ? bit 6 (/pd6) control bit is used to enable the pull-down of p62 pin. ? bit 7 (/pd7) control bit is used to enable the pull-down of p63 pin. ? iocb register is both readable and writable. 6. iocc (open-drain control register) 7 6 5 4 3 2 1 0 o d 7 o d 6 o d 5 o d 4 o d 3 o d 2 o d 1 o d 0 ? bit 0 (od0) control bit is used to enable the open-drain of p60 pin. 0: disable open-drain output 1: enable open-drain output ? bit 1 (od1) control bit is used to enable the open-drain of p61 pin. ? bit 2 (od2) control bit is used to enable the open-drain of p62 pin. ? bit 3 (od3) control bit is used to enable the open-drain of p63 pin. ? bit 4 (od4) control bit is used to enable the open-drain of p64 pin. ? bit 5 (od5) control bit is used to enable the open-drain of p65 pin. ? bit 6 (od6) control bit is used to enable the open-drain of p66 pin. this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 13
em78p156el otp rom ? bit 7 (od7) control bit is used to enable the open-drain of p67 pin. ? iocc register is both readable and writable. 7. iocd (pull-high control register) 7 6 5 4 3 2 1 0 / p h 7 / p h 6 / p h 5 / p h 4 / p h 3 / p h 2 / p h 1 / p h 0 ? bit 0 (/ph0) control bit is used to enable the pull-high of p60 pin. 0: enable internal pull-high 1: disable internal pull-high ? bit 1 (/ph1) control bit is used to enable the pull-high of p61 pin. ? bit 2 (/ph2) control bit is used to enable the pull-high of p62 pin. ? bit 3 (/ph3) control bit is used to enable the pull-high of p63 pin. ? bit 4 (/ph4) control bit is used to enable the pull-high of p64 pin. ? bit 5 (/ph5) control bit is used to enable the pull-high of p65 pin. ? bit 6 (/ph6) control bit is used to enable the pull-high of p66 pin. ? bit 7 (/ph7) control bit is used to enable the pull-high of p67 pin. ? iocd register is both readable and writable. 8. ioce (wdt control register) 7 6 5 4 3 2 1 0 w d t e e i s - r o c - - - - ? bit 7 (wdte) control bit used to enable watchdog timer. 0: disable wdt. 1: enable wdt. wdte is both readable and writable. ? bit 6 (eis) control bit is used to define t he function of p60 (/int) pin. 0: p60, bi-directional i/o pin. 1: /int, external interru p t pin. in this ca se, the i/o cont rol bit of p60 (bit 0 of ioc6) must be set to "1". whe n eis is " 0 ", the path of /int is m a sked. wh en ei s is "1", the sta t us of /int pi n can also b e read by way of reading port 6 (r6). refer to fig. 7(a). eis is both readable and writable. ? bit 4 (roc) roc is used for the r-option. setting the roc to "1" wil l enable th e status of r-o p tion pin s (p 50 ?
em78p156el otp rom ? bits 0~3,5 not used. 9. iocf (interrupt mask register) 7 6 5 4 3 2 1 0 - - - - - e x i e i c i e t c i e ? bit 0 (tcie) tcif interrupt enable bit. 0: disable tcif interrupt 1: enable tcif interrupt ? bit 1 (icie) icif interrupt enable bit. 0: disable icif interrupt 1: enable icif interrupt ? bit 2 (exie) exif interrupt enable bit. 0: disable exif interrupt 1: enable exif interrupt ? bits 3~7 not used. ? individual interrupt is enabled by setting its a ssociated control bit in the iocf to "1". ? global inte rrupt is en able d by the eni instru ction a nd i s di sabl ed by the disi in struction. refer t o fig. 10. ? iocf register is both readable and writable. 4.3 tcc/wdt & prescaler an 8-bit cou n t er availabl e as p r e s cale r for the t cc or wdt. th e pre s cale r is available fo r either the tcc or wdt only at any given time, and the pab b i t of the cont register is used to determine the pre s cale r assi gnme n t. the psr0~ps r2 bits determin e t he ratio. th e pre s cale r is clea re d ea ch time the instructio n is written to tcc un de r t c c mode. t he wdt an d p r e s cale r, wh en assign ed to wdt mod e , are cleared by the ?wdtc? or ?slep? instructions. fig. 5 depicts the circui t diagram of tcc/wdt. ? r1 (t cc) is an 8-bit time r/co unte r . the clo ck so urce of tcc can be intern al o r external clo ck in put (edge select able from t cc pin). if t cc signal source is from internal clock, t cc will increase by 1 at every instru cti on cycle (with out pr e s cale r). referrin g to fig. 5, clk=f o sc/2 or clk = fo sc/4 appli c ation is dete r min e d by the co de optio n bi t clk st at us. clk=f o sc/ 2 is u s ed if clk bit i s " 0 ", and clk = fo sc/4 i s u s ed if clk bit is "1". if tcc si gnal source com e s from exter nal clo ck i nput, tcc is increased by 1 at every falling edge or rising edge of tcc pin. ? the watch d og timer is a free ru nni ng o n -chip rc oscillato r . the wdt will kee p on runni ng even when the oscillator driver h a s b e en turne d of f (i.e. in sleep m ode ). duri ng norm a l ope rat i on or sl eep mode, a wdt time-ou t (if enabl ed ) will cau s e th e device to reset. the wdt can be ena bl ed o r di sabl e d any this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 15
em78p156el otp rom time durin g n o rmal m ode by sof t wa re pro g ra mming . refer to wdte bit of ioce re giste r . without prescaler , the wdt time-out period is approximately 18 ms 1 (default). wd t te tcc 8-b i t c o u n te r 2 cy cles tcc ( r 1 ) syn c pin m x u m x u m x u 8-t o -1 m u x mux ts 0 ps r 0 ~ p s r 2 wd t t i m e - o u t pa b t c c o v e r f l o w in te r r u p t c l k( = f osc / 2 or f o sc /4) pa b (i n i o c e ) wt e dat a b u s pa b 1 0 1 0 1 01 i o ca m x u i n it ial va l u e pa b fig. 5 block diagram of tcc and wdt 4.4 i/o ports the i/o re gist ers, both po rt 5 and po rt 6, are bi -di r e c ti onal tri - state i / o port s . port 6 ca n be pull ed hig h intern ally by softwa r e. in addition, po rt 6 can also h a ve ope n-d r a i n output by softwa r e. inp u t status cha nge inte rrupt (or wa ke-up) fun c tion o n port 6. p50 ~ p52 and p6 0 ~ p63 pin s can b e pulle d down by softwa r e. each i/o pin can be defined a s "input" or "out put" pin by the i/o control registe r (ioc5 ~ ioc6). p50~p5 1 are the r-o p tion pins e nabl ed by setting t he ro c bit in the ioce re g i ster to 1. when the r-option fun c tion is use d , it is reco mmen ded that p50~ p51 are use d as output pi ns. whe n r-o p tion is in enabl e state, p50~p5 1 mu st be prog ra mmed as inp u t pins. unde r r-o p tion m ode, the current/power consumption by rex should be taken into the c onsideration to promote energy conservation. the i/o regist ers and i/o control re giste r s are both re adabl e and writable. the i/o interface ci rcuits for port 5 and port 6 are shown in the followi ng figures 6, 7(a), 7(b), 7(c)and figure 8. 1 : vdd = 5v, set up time period = 16.8ms 30% vdd = 3v, set up time period = 18ms 30% this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 16
em78p156el otp rom pc w r p crd pd w r p drd io d 0 1 m u x po r t q q _ d d q q _ cl k p r c l clk p r c l note: pull-down is not shown in the figure. fig. 6 the circuit of i/o port a nd i/o control register for port 5 p crd io d pc w r pd w r pd r d bi t 6 o f i o c e po r t p6 0 / i n t t1 0 in t m u x 0 1 cl k cl k cl k cl k p p p p r r r r c l l l l c c c q q q q q q q q d d d d _ _ _ _ note: pull-high (down) and open-drain are not shown in the figure. fig. 7(a) the circuit of i/o port a nd i/o control register for p60 (/int) this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 17
em78p156el otp rom p crd pc wr pd w r pd r d tin iod p 61~p 6 7 po r t 0 1 m u x cl k clk clk p p p l l l r r r c c c d d d q q q q q q _ _ _ note: pull-high (down) and open-drain are not shown in the figure. fig. 7(b) the circuit of i/o port and i/o control register for p61~p67 /slep t17 t10 t11 ioce.1 interrupt eni instruction disi instruction interrupt (wake-up from sleep) next instruction (wake-up from sleep) clk clk clk q q q q q q _ _ _ d d d p p p l l l r r r c c c re.1 fig. 7(c) block diagram of i/o port 6 w i th input change interrupt/w ake-up this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 18
em78p156el otp rom table 4 usage of port 6 input change wake-up/interrupt function usage of port 6 input status changed wake-up/interrupt (i) wake-up from port 6 input status change (ii) port 6 input status change interrupt (a) before sleep 1. read i/o port 6 (mov r6,r6) 1. disable wdt 1 (using very carefully) 2. execute "eni" 2. read i/o port 6 (mov r6,r6) 3. enable interrupt (set iocf.1) 3. execute "eni" or "disi" 4. if port 6 change (interrupt) 4. enable interrupt (set iocf.1) interrupt vector (008h) 5. execute "slep" instruction (b) after wake-up 1. if "eni" interrupt vector (008h) 2. if "disi" nex t inst ruct ion vcc roc p crd pc w r iod pd w r p drd we a k l y p u ll-u p po r t q q p r c l d clk q q d p r c l m u x rex * 1 0 *t he re x i s 430k ohm ex t ern al r e s i st or fig. 8 the circuit of i/o port w i th r-option(p50,p51) 1 note: software disables wdt (watchdog ti mer) but hardware must be enabled before applying port 6 change wake-up function. (code option register and bit 11 (enwdtb-) set to ?1?). this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 19
em78p156el otp rom 4.5 reset and wake-up 1. reset a reset is initiated by one of the following events- (1) power on reset. (2) /reset pin input "low", or (3) wdt time-out (if enabled). the device is kept in a reset condition for a period of approx. 18ms 1 (one o scillator sta r t-up timer period) after t he reset is detec t ed. once the r eset occ u rs , the following func t i ons are perf ormed. refer to fig.9. ? the oscillator is running, or will be started. ? the program counter (r2) is set to all "0". ? all i/o port pins are configured as input mode (high-impedance state). ? the watchdog timer and prescaler are cleared. ? when power is switched on, the upper 3 bits of r3 are cleared. ? the bits of the cont register are set to all "1" except for the bit 6 (int flag). ? the bits of the ioca register are set to all "1". ? the bits of the iocb register are set to all "1". ? the iocc register is cleared. ? the bits of the iocd register are set to all "1". ? bit 7 of the ioce register is set to "1", and bits 4 and 6 are cleared. ? bits 0~2 of rf and bits 0~2 of iocf register are cleared. the sle ep (po w e r down) m ode is asse rt ed by execut ing the ?slep? instru ction. while ente r in g slee p mode, wdt (if enabled) is cleared but keeps on running. the controller can be awakened by- (1) external reset input on /reset pin, (2) wdt time-out (if enabled), or (3) port 6 input status changes (if enabled). the first two ca se s will ca use th e em7 8 p156el to reset. th e t a nd p flags of r3 can be u s ed t o determi ne the sou r ce of the reset (wa k e - up). the la st ca se is con s i dered the con t inuation of program executio n an d the glo bal interrupt ("e n i" or " d isi" being execu t ed) d e ci de s wheth e r or n o t the 1 note: vdd = 5v, set up time period = 16.8ms 30% vdd = 3v, set up time period = 18ms 30% this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 20
em78p156el otp rom cont rolle r bra n ch es to the interrupt vect or follo wing wa ke -up. if eni is exe c ute d before sle p , the instructio n will begin to execute from th e addre s s 00 8h after wa ke-u p. if disi is execute d before slep, the operation will restart from the succeeding instruction right next to slep after wake-up. only one of cases 2 and 3 can be enabled bef ore entering the sleep mode. that is, [a] if port 6 input status cha nge interrupt is enabl ed before sl ep , wdt must be disa bl ed. b y softwa r e. ho weve r, the wdt bit in the opt ion regi ster re main s ena bl ed. he nce, the em78p156el can be awakened only by case 1 or 3. [b] if wdt is enabl ed before slep, port 6 input st atu s cha nge interrupt mu st be disabl ed. hence, the em78p156el can be awakened only by case 1 or 2. refer to the section on interrupt. if port 6 input status cha nge interrupt is use d to wake -up the em78p15 6el (case [a] above), the following instructions must be executed before slep: mov a, @xx000110b ; select internal tcc clock contw clr r1 ; clear tcc and prescaler mov a, @xxxx1110b ; select wdt prescaler contw wdtc ; clear wdt and prescaler mov a, @ 0 xxxxxxxb ; d i s able w d t iow re mov r6, r6 ; read port 6 mov a, @00000x1xb ; enable port 6 input change interrupt iow rf eni (or disi) ; enable (or disable) global interrupt slep ; sleep nop one p r obl em use r sh ould be aware of, is that a fter wa king u p from the sle e p mode, wdt would enabl e auto m atically. the wdt ope ration (b ei ng enabled or disable d ) should be ha ndle d appropriately by software after waking up from the sleep mode. this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 21
em78p156el otp rom table 5 the summary of the initialized values for registers address name reset t y pe bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit name x x x x c53 c52 c51 c50 pow e r - o n u u u u 1 1 1 1 /reset and wdt u u u u 1 1 1 1 n / a i o c 5 w a ke-up from pin change u u u u p p p p bit name c67 c66 c65 c64 c63 c62 c61 c60 pow e r - o n 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 n / a i o c 6 w a ke-up from pin change p p p p p p p p bit name x /int ts te pab psr2 psr1 psr0 pow e r - o n 1 0 1 1 1 1 1 1 /reset and wdt 1 0 1 1 1 1 1 1 n / a c o n t w a ke-up from pin change p p p p p p p p bit name - - - - - - - - pow e r - o n u u u u u u u u /reset and wdt p p p p p p p p 0 x 0 0 r 0 ( i a r ) w a ke-up from pin change p p p p p p p p bit name - - - - - - - - pow e r - o n 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0 x 0 1 r 1 ( t c c ) w a ke-up from pin change p p p p p p p p bit name - - - - - - - - pow e r - o n 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0 x 0 2 r 2 ( p c ) w a ke-up from pin change **0/p **0/p **0/p **0/p **1/p **0/p **0/p **0/p bit name gp2 gp1 gp0 t p z dc c pow e r - o n 0 0 0 1 1 u u u /reset and wdt 0 0 0 t t p p p 0 x 0 3 r 3 ( s r ) w a ke-up from pin change p p p t t p p p bit name - - - - - - - - pow e r - o n 1 1 u u u u u u /reset and wdt 1 1 p p p p p p 0 x 0 4 r 4 ( r s r ) w a ke-up from pin change 1 1 p p p p p p bit name x x x x p53 p52 p51 p50 pow e r - o n 0 0 0 0 u u u u /reset and wdt 0 0 0 0 p p p p 0 x 0 5 p 5 w a ke-up from pin change 0 0 0 0 p p p p bit name p67 p66 p65 p64 p63 p62 p61 p60 pow e r - o n u u u u u u u u 0 x 0 6 p 6 /reset and wdt p p p p p p p p this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 22
em78p156el otp rom address name reset t y pe bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w a ke-up from pin change p p p p p p p p bit name x x x x x ex if icif tc i f pow e r - o n u u u u u 0 0 0 /reset and wdt u u u u u 0 0 0 0x0f r f ( i s r ) w a ke-up from pin change u u u u u p p p bit name - - - - - - - - pow e r - o n 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 0 x 0 a i o c a w a ke-up from pin change p p p p p p p p bit name /pd7 /pd6 /pd5 /pd4 x /pd2 /pd1 /pd0 pow e r - o n 1 1 1 1 u 1 1 1 /reset and wdt 1 1 1 1 u 1 1 1 0 x 0 b i o c b w a ke-up from pin change p p p p u p p p bit name od7 od6 od5 od4 od3 od2 od1 od0 pow e r - o n 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 0 x 0 c i o c c w a ke-up from pin change p p p p p p p p bit name /ph7 /ph6 /ph5 /ph4 /ph3 /ph2 /ph1 /ph0 pow e r - o n 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 0 x 0 d i o c d w a ke-up from pin change p p p p p p p p bit name wdt e eis x roc x x x x pow e r - o n 1 0 u 0 u u u u /reset and wdt 1 0 u 0 u u u u 0 x 0 e i o c e w a ke-up from pin change 1 p u p u u u u bit name x x x x x ex ie icie tc i e pow e r - o n u u u u u 0 0 0 /reset and wdt u u u u u 0 0 0 0x0f i o c f w a ke-up from pin change u u u u u p p p bit name - - - - - - - - pow e r - o n u u u u u u u u /reset and wdt p p p p p p p p 0x10~ 0x2f r 1 0 ~ r2f w a ke-up from pin change p p p p p p p p ** to jump address 0x08, or to execute the instruct ion which is next to the ?slep? instruction. x: not used. u: unknown or don?t care. p: previous value before reset. t: check table 6 2. the status of rst, t, and p of status register a reset condition is initiated by the following events: 1. a power-on condition, 2. a high-low-high pulse on /reset pin, and this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 23
em78p156el otp rom 3. watchdog timer time-out. the value s o f t and p, listed in table 6 are u s e d to che ck h o w t he processo r wakes u p . table 7 shows the events that may affe ct the status of t and p. table 6 the values of rst, t and p after reset reset type t p power on 1 1 /reset during operating mode *p *p /reset wake-up during sleep mode 1 0 wdt during operating mode 0 *p wdt wake-up during sleep mode 0 0 wake-up on pin change during sleep mode 1 0 *p: previous status before reset table 7 the status of t and p being affected by ev ents. event t p power on 1 1 wdtc instruction 1 1 wdt time-out 0 *p slep instruction 1 0 wake-up on pin change during sleep mode 1 0 *p: previous value before reset v o l t age d e t ect o r po w e r - o n r ese t wd t e set u p t i m e vdd dq cl k clr cl k res e t wd t t i m e o u t wd t /r e s e t o sci l l at o r fig. 9 block diagram of controller reset this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 24
em78p156el otp rom 4.6 interrupt the em78p156el has three falling-edge interrupts listed below: (1) tcc overflow interrupt (2) port 6 input status change interrupt (3) external interrupt [(p60, /int) pin]. before the port 6 input status cha nge interrupt is enabl ed, rea d ing port 6 (e.g. "mov r 6 ,r6") is necessa ry. each pin of port 6 will hav e this feature if i t s status chan ged. any pin config ured as output or p60 pin confi gured a s /int is exclud ed from this fun c tion. the port 6 input st atus chan ged int e rrupt ca n wa ke up th e em78p15 6el from the sl e ep mod e if port 6 is ena bled prior to g o ing into the slee p mode by executin g slep. when the chip wa ke s-up, the co ntrolle r will cont inue to ex ecute the su cceedi ng add re ss if the global interru p t is disabl ed or bra n ch to the interrupt vecto r 008 h if the global int e rrupt is enabled. rf is the i n te rru pt status re giste r t hat re cord s the inte rrupt req u e s ts i n the relative flags/bits. io cf is a n interrupt ma sk regi ster. th e glob al inte rrupt is e nabl ed by the eni in stru ction and i s di sabl ed by the disi instructio n. whe n one of the interru pts (en able d ) occu rs, the n e xt instructi o n will be fetched from add re ss 00 8 h . once in the interrupt se rvice routine, the sou r ce of an interrupt can b e determined by polling the flag bits in rf . the interru pt flag bit mu st be cle a re d by instructi ons befo r e le aving the interrupt service routine and before interrupt s are enabled to avoid recursive interrupts. the flag (except icif bit) in the interrup t status regist er (rf) is set regardle ss of the status of its mask bit or the execution of eni. note that the outcom e of rf will be the logic a nd of rf and iocf (refer to fig. 10). the reti instru ction end s the interrupt routi ne and ena bl es the global i n terrupt (the executio n of eni). whe n an interru pt is gene rated by the in t instru cti on (enabl ed ), the next instru ctio n will be fetched from address 001h. this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 25
em78p156el otp rom int eni / di s i io d rfw r iocfrd io c f w r irqn irqm rf r d iocf / r es et /i r q n vcc rf clk clk q q d p r l c _ p r l c q q _ d fig. 10 interrupt input circuit 4.7 oscillator 1. oscillator modes the em78p1 56el can be ope rated in th ree different o sc ill ator mo de s, su ch a s extern al rc osci llator mode (erc), high xtal oscillato r mo de (hxt), an d lo w xtal oscillato r mo de (lxt). user ca n sele ct one of them by prog rammi ng ms and hl f in the code opti on regi ster. t able 8 depi ct s how these three modes are defined. the up-mo st limited operation frequ en cy of crystal/re sonato r on the different vdds is liste d in table 9. table 8 oscillator modes defined by ms and hlp mode ms hlf hlp erc(external rc oscillator mode) 0 *x *x hxt(high xtal oscillator mode) 1 1 *x lxt(low xtal oscillator mode) 1 0 0 1. x, don?t care 2.the transient point of system fr equency between hxt and lxy is around 400 khz. this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 26
em78p156el otp rom table 9 the summary of maximum operating speeds conditions vdd fxt max.(mhz) 2 . 3 4 . 0 3 . 0 8 . 0 two cy cles wit h t w o clocks 5 . 0 2 0 . 0 2. cry s tal oscillator/cera mic resonators (xtal) em78p15 6el can be d r iv en by an extern al clo ck si gnal thro ugh the osci pin as sho w n in fig. 11 below. os ci os co em78p156el ex t. cloc k fig. 1 1 circuit for external clock input in the most a pplication s , pi n osci an d p i n osco ca n con n e c t ed wi t h a cry s t a l o r cer a mi c re so nat or to gene rate o scill ation. fig. 12 de pict s such circui t. the same thin g appli e s wh ether it is i n the hx t mode or in th e lxt mo de. table 10 p r o v ides the re commen ded v a lue s of c1 a nd c2. since each re son a tor h a s its own attrib ute, use r sho u ld refer to its spe c ification for ap pro p ri ate value s of c1 a n d c2. rs, a serial resistor, may be necessary fo r at strip cut crystal or low frequency mode. os ci os co em78p156el c1 c2 xt a l rs fig. 12 circuit for cry s t a l/resonator this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 27
em78p156el otp rom table 10 capacitor selection guide for cry s tal oscillator or ceramic resonator oscillator type frequency mode frequency c1(pf) c2(pf) 455 khz 100~150 100~150 2.0 mhz 20~40 20~40 ceramic resonators hxt 4.0 mhz 10~30 10~30 3 2 . 7 6 8 k h z 2 5 1 5 1 0 0 k h z 2 5 2 5 lxt 2 0 0 k h z 2 5 2 5 4 5 5 k h z 2 0 ~ 4 0 2 0 ~ 1 5 0 1 . 0 m h z 1 5 ~ 3 0 1 5 ~ 3 0 2 . 0 m h z 1 5 1 5 crystal oscillator hxt 4 . 0 m h z 1 5 1 5 3. external rc oscillator mode for som e applications that do not need a very preci s e timing cal c ulat ion, the rc oscillator (fig. 15) offers a lot of co st savin g s. neve rthele s s, it shoul d be noted that the frequ en cy of the rc o scill a t or i s influen ced by the supply voltage, the values of the re sisto r (rext), the cap a cito r (cext), and e v en by the operation temperatu r e. moreove r , the freque ncy also cha nge s slightly from one chip to anothe r due to the manufacturing process variation. in orde r to maintain a stab le system fre quen cy, t he value s of the cext sho u ld n o t be less tha n 20pf, and that the value of rext should not be gre a ter than 1 m ohm. if they cannot be kept in this ran ge, the frequency is easily affected by noise, humidity, and leakage. the sm alle r the rext in the rc o s cillator, the faster its freque ncy wil l be. on the contra ry, for very lo w rext values, for instance , 1 k ?
em78p156el otp rom os ci e m 78p156e l vc c rext cext fig. 13 circuit for external rc oscillator mode table 11 rc oscillator frequencies cex t rex t average fosc 5v,25 q c average fosc 3v,25 q c 3.3k 3.92 mhz 3.65 mhz 5.1k 2.67 mhz 2.60 mhz 1 0 k 1 . 3 9 m h z 1 . 4 0 m h z 20 pf 100k 149 khz 156 khz 3.3k 1.39 mhz 1.33 mhz 5.1k 940 khz 920 khz 10k 480 khz 475 khz 100 pf 100k 52 khz 50 khz 3.3k 595 khz 560 khz 5.1k 400 khz 390 khz 10k 200 khz 200 khz 300 pf 100k 21 khz 20 khz 1. measured on dip packages. 2. for design reference only. 3. the frequency drift is about ? 30% 4.8 code option register the em78p 1 56el ha s a co de option word that is not a pa rt of the normal p r ogram mem o ry. the option bits cannot be accessed during normal program execution. code option register and customer id register arrangement distribution: this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 29
em78p156el otp rom word 0 word 1 bit12~ b i t 0 b i t 1 2 ~ b i t 0 1. code option register (word 0) word 0 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ms /enwdt clk cs hlf - hlp - - - - - - ? bit 12 (ms ):oscillator type selection. 0: rc type 1: xtal type (xtal1 and xtal2) ? bit 11 (/enwdt) : watchdog timer enable bit. 0: enable 1: disable ? bit 10 (clk) : instruction period option bit. 0: two oscillator periods. 1: four oscillator periods. refer to the section on instruction set. ? bit 9 (cs) : code security bit 0: sec u rity on 1: sec u rity off ? bit 8 (hlf) : xtal frequency selection 0: xtal2 type (low frequency, 32.768khz) 1: xtal1 type (high frequency) this bit will affect system oscillation only when bit 12 (ms) is ?1?. when ms is?0?, hlf must be ?0?. : the transient point of system frequency between hxt and lxy is around 400 khz. ? bit 7 : reserved. the bit s e t to ?1? all the time. ? bit 6 (hlp) : p o wer select ion. 0: low power 1: high power ? bit 5~0 : customer?s id code 2. customer id register (word 1) bit 12~bit 0 xxxxxxxxxxxxx ? bit 12~0: customer?s id code this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 30
em78p156el otp rom 4.9 power on considerations any microcon troller i s n o t g uarantee d to start to o per a t e pro perly b e fore th e po wer sup p ly sta y s at its steady state. em78p15 6el por voltage rang e is 1.2 v ~1.8v. und e r cu stome r a pplication, wh en power is off, vdd must drop to belo w 1.2v and rem a in s off for 10u s b e fore po we r can be switch e d on agai n. this way, the em78p15 6el will re set and work no rmally. the ex tra extern al reset circuit wi ll work well if vdd ca n rise at very fast spe ed (5 0 ms or less). howeve r, unde r most ca se s whe r e critical appli c ati ons a r e involved, extra devices are required to a ssist in solving the power-up problems. 4.10 external power on reset circuit the circuit sh own in fig.16 impleme n ts a n external rc to produ ce th e reset pul se. the pulse wid t h (time con s tant ) sho u ld be kept long en oug h for vdd to re a c he d minimu m operation voltage. this circuit is use d wh en the power supp ly has slo w ri se time. be ca use the curre n t leaka ge fro m the /reset pin is about em78p156el / reset vdd d r rin c fig. 14 external pow e r-up reset circuit 4.11 residue-voltage protection whe n battery is replace d , device po we r (vdd) i s taken off but resid u e - vo ltage rem a in s. the re sidu e-volta ge may trips belo w vdd m i nimum, but not to zero. this conditio n may cau s e a poor this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 31
em78p156el otp rom power on reset. fig.18 and fig. 19 show how to build a residue-voltage protection circuit. em78p156el /reset vdd 40k q1 1n4684 10k 33k vdd fig. 15 circuit 1 for the residue v o lt age protection em78p156el / reset vdd q1 vdd 40k r2 r1 fig. 16 circuit 2 for the residue v o lt age protection 4.12 instruction set each in stru ction in the instru ction set is a 13- bit word divided into an op cod e and one or more ope ran d s. normally, all in stru ct ion s are executed within one singl e instru ction cycle (one in structio n con s i s ts of 2 oscillato r peri ods), unle ss t he pro g ra m counte r is ch a nged by inst ruction "mov r2,a", "add r2,a", or by instructi ons of arith m etic or logi c o peration on r2 (e.g. "sub r2,a", "bs(c) r2,6", this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 32
em78p156el otp rom "clr r2", ????
em78p156el otp rom 0 0010 00rr rrrr 02rr or a,r a ?
em78p156el otp rom 4.13 timing diagrams reset timin g ( c lk= " 0") clk / r es et nop in struc t ion 1 e x ecu te d td r h tc c in put timing (clks= "0") clk tc c tt c c ti n s a c t esti ng : inpu t is d r iv en at 2. 4v for lo gic "1 ", and 0 . 4v fo r l ogic "0".t i min g meas u r ement s are made at 2.0v f o r logi c "1", a n d 0. 8 v f o r log i c "0". a c tes t i n put/output wav e form 2.4 0.4 2.0 0.8 t est poi n t s 2. 0 0. 8 this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 35
em78p156el otp rom 5. absolute maximunm ratings items rating temperature under bias 0
em78p156el otp rom 6. electrical characteristics 6.1 dc electrical characteristic ( ta= 25 ? % %
em78p156el otp rom 6.2 ac electrical characteristic (ta=25
em78p156el otp rom 6.3 device characteristic the gra p h s provide d in the following pa ges were deri v ed base d on a limited number of sam p les an d are sho w n h e re for referen c e only. the device charact e ri stic illust ra ted herei n are not guaran teed for it accuracy. in some graphs, the data maybe out of the specified warranted operating range. vih/vil (input pins with schmitt inverter) 0 0. 5 1 1. 5 2 2. 5 2. 5 3 3. 5 4 4. 5 5 5. 5 vd d(vo lt) vih vil(volt) vih max (0 j to 70 j ) vih typ 25 j vih min (0 j to 70 j ) vil max (0 j to 70 j ) vil typ 25 j vil min (0 j to 70 j ) fig. 17 vih, vil of port6 v s . vdd this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 39
em78p156el otp rom v t h ( i n put t h e r s h ol d vol t a g e ) of i / o pi ns 0 0. 2 0. 4 0. 6 0. 8 1 1. 2 1. 4 1. 6 1. 8 2. 5 3 3. 5 4 4. 5 5 5. 5 vdd( vo l t ) vth(volt) typ 25 j max(0 j to 70 j ) min(0 j to 70 j ) fig. 18 vth (threshold v o ltage) of port5 v s . vdd this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 40
em78p156el otp rom voh/ i o h ( vdd=5v) -2 5 -2 0 -1 5 -1 0 -5 0 01 23 45 voh( volt) ioh(ma) voh/ioh (vdd=3v) -6 -4 -2 0 0 0 .5 1 1 .5 2 2 .5 3 v oh( v o l t ) ioh(ma ) min 70 j typ 25 j min 0 j min 70 j typ 25 j m in 0 j fig. 19 port5 and port6 voh v s . ioh, vdd=5v fig. 20 port5 and port6 voh v s . ioh, vdd=3v
em78p156el otp rom vo l/io l (vdd=5 v ) 0 10 20 30 40 50 60 70 80 01 23 45 vo l(vo lt) iol(ma) vol/iol (vdd=3v) 0 5 10 15 20 25 30 35 00 . 511 . 5 22 . 5 3 v o l(v o lt) iol(ma) max 0 j max 0 j typ 25 j typ 25 j min 70 j min 70 j fig. 21 port5, port6 vol v s . iol, vdd = 5v fig. 22 port5, port6 vol v s . iol, vdd = 3v this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 42
em78p156el otp rom wdt tim e _out 0 5 10 15 20 25 30 234 56 vdd (vo lt) wdt period (ms) max 7 0 j typ 25 j min 0 j fig. 23 wdt time out period v s . vdd, perscaler set to 1:1 this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 43
em78p156el otp rom this specification is subject to cha nge w i thout prio r notice. 44 07.29.2004 (v1.3) cex t = 100pf , typical rc f requency vs. vdd 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 2 . 533 . 544 . 555 . 5 vdd( volt) frequency(m hz) r = 3.3k r = 5.1k r = 10k r = 100k fig. 24 ty pical rc osc frequency v s . vdd (cext= 100pf, temperature at 25 j ) vdd = 5v vdd = 3v fig. 25 ty pical rc osc frequency v s . vdd (r and c are ideal components)
em78p156el otp rom four conditions exist with the operating current icc1 to icc4. these conditions are as follows: i cc1: v dd=3v , fosc=32k hz, 2 clocks, wdt disable icc2: vdd=3v, fosc=32k hz, 2 clocks, wdt enable icc3: vdd=5v, fosc=4m hz, 2 clocks, wdt enable icc4: vdd=5v, fosc=10m hz, 2 clocks, wdt enable typical icc1 and icc2 vs. temperature 9 10 11 12 13 14 15 0 1 0 2 03 0 4 05 0 6 07 0 t e mper a t ur e ( j ) current (ua) t yp icc2 t yp icc1 fig. 26 ty pical operating current (icc1 and icc2) v s . temperature max i mum icc1 and icc2 vs. temperature 14 15 16 17 18 19 20 21 0 1 02 03 0 4 05 06 07 0 t e mper atur e ( j ) current (ua) max icc2 max icc1 fig. 27 maximum operating current (icc1 and icc2) v s . temperature this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 45
em78p156el otp rom t y pi c a l i c c 3 a nd i c c 4 v s . t e m p e r a t ur e 0 0. 5 1 1. 5 2 2. 5 3 3. 5 4 0 1 02 03 04 05 06 07 0 t e m p er at u r e ( j ) current (ma) t yp icc4 t yp icc3 fig. 28 ty pical operating current (icc3 and icc4) v s . temperature max i mum icc3 and icc4 vs. temperature 1 1. 5 2 2. 5 3 3. 5 4 0 1 0 2 03 04 05 0 6 07 0 t e mper atur e ( j ) current (ma) max icc4 max icc3 fig. 29 maximum operating current (icc3 and icc4) v s . temperature this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 46
em78p156el otp rom two conditions exist with the standby current i sb1 and isb2. these condi tions are as follows: isb1: vdd=5v, wdt disable isb2: vdd=5v, wdt enable typical isb 1 and isb 2 vs. temperature 0 2 4 6 8 10 0 1 02 0 3 04 0 5 06 0 7 0 temperature ( j ) current (ua) t yp isb2 t yp isb1 fig. 30 ty pical standby current (isb1 and isb2) v s . temperature maxim u m isb1 and isb2 vs. tem p erature 0 2 4 6 8 10 0 1 02 03 0 4 05 06 07 0 t e mper atur e ( j ) current (ua) max isb2 max isb1 fig. 31 maximum standby current (isb1 and isb2) v s . temperature this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 47
em78p156el otp rom fig. 32 operating v o ltage in temperature range from 0 j to 70 j this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 48
em78p156el otp rom em78p 156e-j hxt v-i 0 0. 25 0. 5 0. 75 1 1. 25 1. 5 1. 75 2 2. 25 2. 5 2. 3 2 . 8 3. 3 3 . 8 4. 3 4 . 8 5. 3 v o ltag e ( v ) i(ma) fig. 33 operating current range (based on high freq. @ =25 j ) v s . voltage em78p156e-j lxt v-i 0 10 20 30 40 50 60 70 2. 3 2 . 8 3. 3 3 . 8 4. 3 4 . 8 5. 3 vo ltag e (v) i(ua) fig. 34 operating current range (based on low freq. @ =25 j ) v s . voltage this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 49
em78p156el otp rom em78p 156e-g hxt v-i 0 0. 25 0. 5 0. 75 1 1. 25 1. 5 1. 75 2 2. 25 2. 5 2. 3 2 . 8 3. 3 3 . 8 4. 3 4 . 8 5. 3 vo ltag e (v) i(ma) fig. 35 operating current range (based on high freq. @ =25 j ) v s . voltage em78p 156e-g lxt v-i 0 10 20 30 40 50 60 70 2.3 2 .8 3.3 3 .8 4.3 4 .8 5.3 voltage(v) i(ua) fig. 36 operating current range (based on low freq. @ =25 j ) v s . voltage this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 50
em78p156el otp rom appendix package ty pes: otp mcu package type pin count package size e m 7 8 p 1 5 6 e l p d i p 1 8 3 0 0 m i l e m 7 8 p 1 5 6 e l m s o p 1 8 3 0 0 m i l e m 7 8 p 1 5 6 e l a s s s o p 2 0 2 0 9 m i l e m 7 8 p 1 5 6 e l k m s s o p 2 0 2 0 9 m i l this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 51
em78p156el otp rom package information 18-lead plastic dual in line (pdip) ?x 300 mil this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 52
em78p156el otp rom this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 53 18-lead plastic small outline (sop) ?x 300 mil
em78p156el otp rom this specification is subject to cha nge w i thout prio r notice. 07.29.2004 (v1.3) 54 20-lead plastic small outline (ssop) ?x 209 mil
em78p156el otp rom this specification is subject to change without prior notice. 07.29.2004 (v1.3) 55 elan (headquarter) microe lectronics corp., ltd. address : no. 12, innovation 1st. rd. science- based industrial park, hsinchu city, taiwan. telephone: 886-3-5639977 facsimile : 886-3-5639966 elan (h.k.) microele ctronics corp., ltd. address : rm. 1005b, 10/f, empire centre, 68 mody road, tsimshatsui, kowloon, hong kong. telephone: 852-27233376 facsimile : 852-27237780 e-mail : elanhk@emc.com.hk elan microelectroni cs shenzhen, ltd. address : ssmec bldg. 3f , gaoxin s. ave. 1st , south area , shenzhen high-tech industrial park., shenzhen telephone: 86-755-26010565 facsimile : 86-755-26010500 elan microelectroni cs shanghai, ltd. address : #23 building no.115 lane 572 bibo road. zhangjiang, hi-tech park, shanghai telephone: 86-21-50803866 facsimile : 86-21-50804600 elan information technology group. address: 1821 saratoga avenue, suite 250, saratoga, ca 95070, usa telephone: 1-408-366-8225 facsimile : 1-408-366-8220 elan microelectronics corp. (europe) address: dubendorfstrasse 4, 8051 zurich, switzerland telephone: 41-43-2994060 facsimile : 41-43-2994079 email : info@elan-europe.com web-site : www.elan-europe.com copyright ? 2004 elan microelectr onics corp. all rights reserved. elan owns the intellectual property rights, concepts, ideas, inventions, know-how (whether patentable or not) related to the information and technology (herein after referred as " information and technology") mentioned above, and all its related indust rial property rights throughout the world, as now may exist or to be created in the future. elan repr esents no warranty for the use of the specifications described, either expressed or implied, including, but not limited, to the implied warranties of merchantability and fitness for particular purposes. th e entire risk as to the quality and performance of the application is with the user. in no even shall elan be liable for any loss or damage to revenues, profits or goodwill or other special, incidental, i ndirect and consequential damages of any kind, resulting from the performance or failure to perform, includi ng without limitation any interruption of business, whatever resulting from breach of contract or breach of warranty, even if elan has been advised of the possibility of such damages. the specifications of the product and its applied technology will be updated or changed time by time. a ll the information and explanations of the products in th is website is only for your reference. the actual specifications and applied technology will be based on each confirmed order. elan reserves the right to modify the informati on without prior notificati on. the most up-to-day information is available on the website http://www.emc.com.tw .

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